Background and scope:
Power consumption and heat dissipation are the most urgent challenges in electronics ranging from mobile devices to large data centres and becomes especially relevant for smart edge devices. Advanced chip designs are lowering energy consumption of microelectronic components, devices and systems, while increasing performance such as speed, capacity, reliability and security. Applications include artificial intelligence, communications, computing and sensing.
Various strategies are and have been tested, but still there is much room to improve energy consumption towards near-fundamental limits, through the co-design of geometry, materials, circuits, and integration in a holistic approach.
The overall goal of this challenge is to explore novel materials and beyond CMOS devices, non-von Neumann architectures and alternative information processing paradigms to drastically reduce energy consumption in order to meet application-specific needs of smart edge devices and circuits.
Specific objectives:
The overall objective of this challenge is to explore solutions (starting at TRL 1/2) that will have a drastic impact on decreasing the power consumption of any smart edge device, but specially for Edge Processing and memories, Edge Sensing and Imaging, Edge Communication and Edge Power Management. The proposed solutions should start at TRL 1-2 and reach TRL 3-4.
The projects, supported under this Challenge are expected to address
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